1. Field of the Invention
The invention relates generally to the field of digital data processing systems, and more specifically to memories for use in such systems that include dynamic random access memory circuit chips that are typically provided in modern digital data processing systems and which periodically must be refreshed to maintain the data stored therein.
2. Description of the Prior Art
A digital data processing system generally includes three basic elements; namely a memory element, an input/output element, and a processor element, all interconnected by one or more buses. The memory element stores data in addressable storage locations. This data includes both operands and instructions for processing the operands. The processor element causes data to be transferred or fetched to it from the memory element, interprets the incoming data as either instructions or operands, and processes the operands in accordance with the instructions. The results are then stored in addressed locations in the memory element. An input/output element also communicates with the memory element in order to transfer data into the system and to obtain the processed data from it. The input/output elements normally operate in accordance with control information supplied to them by the processor element. The input/output elements may include, for example, printers, teletypewriters, or keyboards and video display terminals, and may also include secondary data storage devices such as disk drives or tape drives.
Modern memories provide a number of individually addressable storage locations in dynamic random access memories (RAMs), with each addressable location comprising several, for example, eight, bit (for "binary digit") storage locations. The random access memories are formed from a plurality of integrated circuit chips, with each chip storing one bit of a number of eight-bit byte storage locations. In most known modern memories, the smallest individually-addressable location comprises an eight-bit byte. Each bit storage location of a dynamic RAM is essentially a transistor amplifier having a large internal capacitance, with the presence of an electrical charge in the capacitance indicating, for example, the value "1", and the absence of a charge indicating the binary value of a "0".
Typically, when a storage location is read, the charge condition of the capacitance is destroyed, and the reading circuitry in the dynamic RAM chip includes circuitry that restores the charge to the level prior to the read operation. Over time, however, even in the absence of reading operations, the charge levels in the capacitances may decrease due to leakage, and so they must be restored, that is, "refreshed", to maintain the integrity of the charge, and thus of the value, representing the data stored in the location. Therefore, memories which incorporate dynamic RAM chips have refresh circuitry which iteratively essentially enables the chips to read the locations in the chips, with the on-chip reading circuitry restoring the charge levels to maintain them at minimum levels. Over a period of time, the refresh circuitry enables all of the locations in the RAM chips to be so refreshed.
While system power is on to the entire digital data processing system including the memory, the refresh operation takes place in synchronism with a global system clock that synchronizes operations throughout the entire data processing system. Recently, high performance data processing systems have been provided with an auxilliary power system comprising a battery at least for the memory so that, in case the normal system power fails, the data stored in the memory chips will not be lost. To conserve battery power, the battery power is applied only to the memory and not to the entire system. In that case, however, no system clock is provided to synchronize or time the refresh operation.